The present disclosure generally relates to a voltage controller and, more particularly, to a voltage regulator controller with a high efficiency and related reference voltage adjusting method.
For many power converters, high energy utilization efficiency is the main design objective. For example, the VR12 specification proposed by Intel requires a voltage regulator controller to improve the operating performance of the CPU while maintaining the operating efficiency of a voltage regulator in a light load operation.
FIG. 1 is a simplified functional block diagram of a power control system 100 in the traditional computer. The power control system 100 comprises a processor 110, a voltage control interface 120, and a power converter 130.
When the load of the power control system 100 reduces, the processor 110 transmits a Decay command to the power converter 130 via the voltage control interface 120 to request the power converter 130 to lower the output voltage Vout to a specified voltage level so as to reduce power consumption.
A timing diagram shown in FIG. 2 illustrates the change of output voltage of the power converter 130. In the example of FIG. 2, the processor 110 transmits the Decay command to the power converter 130 at time point T1 to request the power converter 130 to lower the output voltage Vout from an original voltage level VID1 to a lower voltage level VID2.
In order to fulfill the request of the Decay command from the processor 110, the traditional power converter 130 linearly reduces an internal reference voltage Vref for controlling the output voltage Vout to a target voltage level VID2 specified by the Decay command when received the Decay command, and stops the voltage regulation operations. As a result, the output voltage Vout of the power converter 130 would gradually reduce to the target voltage level VID2 due to the current consumption of the load.
When the output voltage Vout of the power converter 130 is reduced to the target voltage level VID2 at a time point T2, the power converter 130 resumes the voltage regulation operations, so that the output voltage Vout can be maintained in or to be close to the target voltage level VID2.
A timing diagram shown in FIG. 3 illustrates the change of output voltage of the power converter 130 in another situation. In the example of FIG. 3, the processor 110 issues a Dynamic Voltage ID (DVID) command to the power converter 130 before the output voltage Vout of the power converter 130 reaches the target voltage level VID2, such as at a time point T3, to request the power converter 130 to pull up the output voltage Vout to another target voltage level VID3. In this situation, the power converter 130 would gradually increase the internal reference voltage Vref from the current voltage level VID2 to the new target voltage level VID3.
When the internal reference voltage Vref of the power converter 130 is increased to be greater than or equal to the current voltage level, VB, of the output voltage Vout for the time being at a time point T4, the power converter 130 resumes the voltage regulation operations to gradually increase the output voltage Vout to the target voltage level VID3.
When the output voltage Vout of the power converter 130 is increased to the new target voltage level VID3 at a time point T5, the power converter 130 performs the voltage regulation operations to maintain the output voltage Vout in or to be close to the target voltage VID3.
In other words, after the processor 110 issues the DVID command, the power converter 130 has to wait for a time period P1 before conducting the voltage regulation operations. Accordingly, a total time length TA (=P1+P2) should be taken for calibrating the output voltage Vout to the new target voltage level VID3, and thus the voltage adjusting speed is limited.
In addition, as shown in FIG. 3, in the period from the time point T3 to the time point T4, during which the internal reference voltage Vref is gradually increased from the voltage level VID2 to the new target voltage level VID3 by the power converter 130, the output voltage Vout of the power converter 130 first gradually reduces from the voltage level VA of the time point T3 to the voltage level VB of the time point T4, and then gradually increases.
However, energy is wasted in the period during which the output voltage Vout of the power converter 130 first decreases and then increases, thereby reducing the energy conversion efficiency of the power converter 130.